Mail: Call for Participation - Early

[Please accept our apologies if you receive multiple copies]
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CALL FOR PARTICIPATION
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We would like to welcome you to participate in
 
XXVII  IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN 2009
Oct 4-7 2009, Resort at Squaw Creek, Lake Tahoe, California
http://iccd.et.tudelft.nl/
 
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IMPORTANT DATES
 
Early registration deadline: Sep 3
Hotel Discount Cut-off date: Setp 3

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PROGRAM AT A GLANCE
http://iccd.et.tudelft.nl/2009/technicalprogram.html
 
[Monday]
 
Keynote I
Monday, October 5, 9:15-10:15
Larrabee a Many-Core Intel ® architecture for visual computing
Roger Espasa, Intel
 
Session I
Monday, October 5, 10:45-12:00
Session 1.1 Disruptive Computing Technology (75 min)
Session 1.2 Advances in Timing Analysis and Optimization (75 min) Yang Xu and Ken Stevens.
Session 1.3 System Power and Thermal Issues (75 min) Soumyaroop Roy, Nagarajan Ranganathan and Srinivas Katkoori.

 
Session II
Monday, October 5, 13:30-15:35
Session 2.1 Disruptive Computer Desig (125 min)
Session 2.2 Hierarchical Testing and Design for Test (125 min)
Session 2.3 Clocking, Synchronization and Interconnect (125 min)
 
Session III
Monday, October 5, 16:00-17:05
Session 3.1 Energy Efficient Architectures (125 min) 
Session 3.2 System Level Test and Verification (125 min)
Session 3.3 Synthesis and Optimization under Reliability Constraints (125 min)
 
Conference Banquet & Keynote II
Monday, October 5, 18:30-21:00
TBA
Mike Liebhold, Institute For Ther Future
 
[Tuesday]
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Keynote III
Tuesday, October 6, 9:00-10:00
TBA
Krisztian Flautner, ARM
 
Session IV
Tuesday, October 6, 10:30-17:05
Session 4.1 High Performance Architecture and Advanced Memory(125 min) Yusuke Tanaka and Hideki Ando.
Session 4.2 Memory and Processors (125 min) Javier Lira, Carlos Molina and Antonio González.
Session 4.3 Disruptive Trends in Test and Verification (100 min)
 
[Wednesday]
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Session V
Wednesday, October 7, 8:30-10:00
Session 5.1 Logic and Memory Design (90 min)
Session 5.2 Application-optimized Systems (90 min) Jiawei Huang and John Lach.

Session VI
Wednesday, October 7, 10:30-12:35
Session 6.1 Novel Approaches to Synthesis and Simulation (125 min)
Session 6.2 System Level Influence on Architecture (125 min)
Session 6.3 Low Voltage and Low Power (125 min)